EDN

Assertion Methodologies for Verilog Design

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...
EDN

An overview of SystemVerilog 3.1

SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along ...
Design-Reuse

Reusing Verilog IP Cores in SystemC Environment by V2SC

SystemC 2.1 supports all hardware concepts introduced by HDLs such as Verilog and VHDL. V2SC proposes a methodology for automatic conversion of Verilog 2001 constructs into SystemC 2.1 language. This ...
Electronic Design

First Commercial Parser Ships For System Verilog

A sure sign that a design language is making its way into the mainstream is the appearance of a spate of tools supporting it. For SystemVerilog devotees, the latest good news is the commercial ...