EDN

System Compiler Adds Support for Mixed-Language Simulation with Verilog and VHDL

San Jose, CA – February 20, 2001 – C Level Design, Inc. today announced a fully automated Verilog Programming Language Interface (PLI) and VHDL Foreign Language Interface (FLI) code generators to ...
EDN

Verilog-2001 language ready to roll

NAPA, Calif. — Implementation of the new Verilog-2001 hardware description language became practical with the IEEE's release Wednesday (Oct. 17) of documentation that describes the standard, ...
Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
Design-Reuse

Open-source core implements MD5 cryptography

SANTA CRUZ, Calif. — Providing a cryptography solution for systems-on-chip, a design and verification engineer has developed an open-source core that implements the MD5 message digest algorithm. The ...