EDN

SpringSoft turns the power of Verdi on SystemVerilog test benches

SystemVerilog was supposed to be such a boon to verification engineers. By providing a Verilog-like language with extensions that made it easy to write transactors, assertions, and checkers, the ...
Semiconductor Engineering

Quality time?

System-Level Design sat down to discuss the future of verification with Olivier Haller, design verification team leader for STMicroelectronics’ functional verification group; Hillel Miller, functional ...
Yahoo Finance

CM Engineering Integrates SpecInsight Family to Silvaco's Logic Simulator Silos to Reduce Verification Debug Time

YOKOHAMA, JAPAN--(Marketwired - April 26, 2016) - CM Engineering Co., Ltd. ("CM Engineering") and Silvaco Japan Co., Ltd. ("Silvaco") have announced that the SpecInsight family of products provided by ...
Design-Reuse

Complex SoC Verification using ARM Processor

Technology evolution, in part, has enabled the transition of multi-million gate designs from large printed circuit boards to SoC (System on Chip). The major advantages of SoC include low cost per gate ...
Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...
Business Insider

Compound Photonics Selects Velocity CAE Design-to-Test Tools From Alliance ATE

SANTA CLARA, CA, Nov. 05, 2019 (GLOBE NEWSWIRE) -- via NEWMEDIAWIRE -- Alliance ATE Consulting Group, Inc. announces today that Compound Photonics U.S. Corporation, a global leader and innovator of ...
Design-Reuse

Using Tcl to create a virtual component in Verilog

It has long been a goal to put realistic prototypes or models into system developer's hands as soon as possible. This has been accomplished with FPGAs, C language models and sometimes co-simulation ...