Design-Reuse

Xilinx In verilog IP Listing

The T-COR-30 FPGA IP core implements the algorithm of automatic tracking of objects in video and calculation of their pa-rameters for solving guidance and target designation tasks. The IP core ... The ...
Hackaday

Yosys Fronts For Xilinx ISE

We always marvel at how open-source tools can often outstrip their commercial counterparts. Yosys, the open-source tool for Verilog synthesis, is a good example. Although the Xilinx ISE design suite ...
Design-Reuse

Xilinx Cache memory design in verilog IP Listing

This Physical Layer core gives you the ability to simultaneously read and write on every rising and falling edge. QDRII+ is a low-latency SRAM-based standard, used in cache coherent systems, ... This ...
Electronics Weekly

Xilinx supports floating-point DSP in 7 Series FPGAs

Xilinx has announced the availability of ISE Design Suite 13.3 featuring new capabilities for DSP designers to implement bit-accurate single, double and full custom precision floating-point math ...
TechRepublic

Implementation of Complex Matrix Inversion Using Gauss-Jordan Elimination Method in Verilog

For high data rate wireless communications they use Orthogonal Frequency Division Multiplexing (OFDM) due to its high spectral efficiency and low computational complexity. It gives the architecture of ...
New Electronics

Everspin and Xilinx team up to address needs of storage industry

Everspin Technologies, a developer and manufacturer of MRAM, has announced a comprehensive design guide to streamline the integration of its 1Gb Spin-transfer Torque Magnetoresistive Random Access ...
Hackaday

Xilinx FPGAs In C For Free

When you think of developing with FPGAs, you usually think of writing Verilog or VHDL. However, there’s been a relatively recent trend to use C to describe what an FPGA should do and have tools that ...