EDN

The VHDL and Verilog story

I put a blog entry up on the Oasys blog about their new release, which is the first to support VHDL. But a couple of people told me it was a nice recounting of history so I decided to put a more ...
EDN

Synopsys pulls VHDL and Verilog together and boosts speed

Synopsys has reworked a number of routines in its VCS hardware simulation tool in an attempt to improve performance at both the gate and RTL level to the point where the company reckons it now has the ...
Design-Reuse

AMIQ EDA Releases the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog ...

AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development, today ...
Electronic Design

VHDL/Verilog Simulator Shows 300% Speed Improvement

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...
Semiconductor Engineering

Customizing An LLM Tailored Specifically For VHDL Code And Design Of High Performance ...

A new technical paper titled “Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors” was published by researchers at IBM. “The use of Large Language Models (LLMs) in ...