GitHub

Export metadata of VHDL to Verilog conversion (synthesis)

Although a structured way to generate names is nice, tools like Surfer can recreate the hierarchy (to some extent). In Surfer, we didn't go for the "reverse-engineer variable name"- approach (as there ...
EDN

The VHDL and Verilog story

I put a blog entry up on the Oasys blog about their new release, which is the first to support VHDL. But a couple of people told me it was a nice recounting of history so I decided to put a more ...
EDN

Synopsys pulls VHDL and Verilog together and boosts speed

Synopsys has reworked a number of routines in its VCS hardware simulation tool in an attempt to improve performance at both the gate and RTL level to the point where the company reckons it now has the ...
Electronic Design

VHDL/Verilog Simulator Shows 300% Speed Improvement

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...
Electronic Design

What’s the Difference Between VHDL, Verilog, and SystemVerilog? (.PDF Download)

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, ...