Design-Reuse

IP Cores, Inc. Announces Two New Multi-Gigabit IP Combo AES/LRW and AES/GCM Cores for System on Chip (SoC) Design

Starting at 30K ASIC gates and delivering up to 10 Gbps throughput, GLM1 and GLM2 cores provide a compact and efficient solution for an SoC designer working on a secure IEEE P1619 storage or IEEE ...
EDN

FPGA IP cores enable flexible SoC design

This product is featured in EDN's Hot 100 products of 2015. See all 100 here. Optimized for TSMC’s 28-nm process, Menta’s predefined off-the-shelf IP cores for complex SoC devices simplify ...
Design-Reuse

Cosmic Circuits targets mixed-signal IP cores for SOC designs in China

Partners with S2C Inc. to bring its silicon-proven IP cores to semiconductor companies in China developing system-on-chips for consumer applications Bengaluru, Karnataka, May 21, 2010 -- Cosmic ...
Hackaday

Xilinx Makes MIPI CSI And DSI Controller IP Blocks Free To Use With Vivado

If you want to use a display or camera with an FPGA, you will often end up with a MIPI-based solution. As of the Xilinx Vivado 2020.1 release, the MIPI DSI (display serial interface) and CSI (camera ...