Design Compiler 2010 also provides RTL designers access to IC Compiler's floorplanning capabilities from within the synthesis environment. With the push of a button, designers can perform what-if ...

Synopsys today introduced Design Compiler® 2010, the latest RTL synthesis innovation within the Galaxy™ Implementation platform, which delivers a twofold speedup in the synthesis and physical ...

By affording access to the IC Compiler floorplanner, this enables what-if analysis of various floorplan options and permits floorplan issues to be addressed in synthesis.

According to Gal Hasson, Senior Director of Marketing for RTL synthesis, power and test automation at Synopsys, DC Explorer has complete script compatibility with standard Design Compiler RTL ...

Said to bring fully automated, accurate timing and block information to front-end integrated IC design, the TOPOMO physical system compiler integrates and automates block partitioning ...

Synopsys, Inc. today announced that AMD is deploying Synopsys' Fusion Compiler™ RTL-to-GDSII product for its full-flow, digital-design implementation. This work has additionally resulted in an ...