Design-Reuse

Efficient logic optimization utilizing complementary behavior of CMOS gates

Any typical digital design style with CMOS uses complementary pairs of p-type and n-type MOSFETs for logic functions implementation. Naturally, CMOS always ought to provide INVERTED outputs like ...
AZoNano

Direct-Write Fabrication of 1D Transistors and Non-CMOS Logic Gates: A Stimulus for Nanoelectronics to Mature

The transistor, an invention that heralded a new era in electronics, is the key component of practically all integrated circuits (ICs) and microprocessors. The point-contact transistor that Walter H.
EDN

Driving CMOS totem poles with logic signals, AC coupling, and grounded gates

Despite massive, large-scale integration being ubiquitous in contemporary electronic design, discrete MOSFETs in the classic CMOS totem pole topology are still sometimes indispensable. This makes tips ...
TechRepublic

Power Optimization of 8:1 MUX Using Transmission Gate Logic (TGL) with Power Gating Technique

In this paper, the authors aim at reducing power and energy dissipation in Transmission Gate Logic (TGL) multiplexer CMOS circuits comprise of reducing the power supply voltages, power supply current ...
The Hindu

Nanomagnet assembly to make up efficient logic gate

A group at Indian Institute of Technology (IIT) Hyderabad has proposed a novel design methodology for constructing an adder logic gate using nanomagnets from magnetic quantum dot cellular automata. At ...
Semiconductor Engineering

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors

“The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have ...