EDN

System Compiler Adds Support for Mixed-Language Simulation with Verilog and VHDL

San Jose, CA – February 20, 2001 – C Level Design, Inc. today announced a fully automated Verilog Programming Language Interface (PLI) and VHDL Foreign Language Interface (FLI) code generators to ...
EDN

Synopsys pulls VHDL and Verilog together and boosts speed

Synopsys has reworked a number of routines in its VCS hardware simulation tool in an attempt to improve performance at both the gate and RTL level to the point where the company reckons it now has the ...
Design-Reuse

Aldec Releases Riviera 2005.04 with All New System-Level Simulation Performance and Debugging

Henderson, Nevada, April 18, 2005 * * * Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of Riviera 2005.04 with an ...
Business Wire

Altium Adds Aldec FPGA Simulation Technology to Altium Designer

SYDNEY--(BUSINESS WIRE)--Altium Limited (ASX:ALU) and Aldec, Inc. have signed an OEM agreement that adds Aldec's FPGA simulation capabilities to Altium Designer. This agreement adds an extra dimension ...
Electronic Design

VHDL/Verilog Simulator Shows 300% Speed Improvement

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...
Design-Reuse

Synopsys speeds Verilog, VHDL simulation

MOUNTAIN VIEW, Calif. — Claiming substantial speedups in its Verilog and VHDL simulation products, Synopsys Inc. this week is announcing releases of its VCS Verilog and Scirocco VHDL simulators. The ...
Ars Technica

Open Source VHDL (or similar) CPU Simulation Software

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...
Hackaday

Using VHDL To Generate Discrete Logic PCB Designs

VHDL and Verilog are hardware description languages, used to describe and define logic circuits. They’re typically used to design ASICs and to program FPGAs, essentially using software to define ...
IEEE

Method of RTL Debugging When Using HLS for HW Design : Different Simulation Result of Verilog & VHDL

Abstract: HLS (High-Level Synthesis) is useful hardware design technologies using High level language (C, C++ and System C) higher than RTL (Register Transfer Level ...