GitHub

Aayush-75/Aayush-75-RISC-V-Processor-Pipeline-Datapath

This project presents a Verilog-based implementation of a 5-stage pipelined RISC-V processor adhering to the RV32I instruction set architecture. The processor is constructed using modular design ...
IEEE

Code Generation for Reconfigurable Explicit Datapath Architectures with LLVM

Abstract: Good tool support is essential for computing platforms because they increase the programmability of the platform. This is especially the case for reconfigurable architectures because an ...
IEEE

OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design

Abstract: OpenRTLSet 1 introduces the largest fully open-source dataset for hardware design, offering over 127,000 diverse Verilog code samples to the research community and industry. Our dataset ...