EDN

Solving FPGA I/O pin assignment challenges

Editor's Note: I've long been impressed by Xcell Journal from Xilinx, both for the quality of its production and the quality of its articles. A few weeks ago we looked at an article on Replacing ...
Hackaday

FreeSoC, For When You Need 68 I/O Pins

Like many of us, [Jon] began his journey through the magical world of microcontrollers with an Arduino. For a beginner, the Arduino is a wonderful tool, but [Jon] quickly found himself limited by the ...
EDN

Binding the “Ties that Break” – Getting FPGA and PCB designers to meet at the I/O pin negotiating table

With their zero NRE and shorter design cycles, FPGA's are steadily replacing ASIC's in mid-level commercial and even higher-volume consumer applications. But as FPGA usage has steadily grown, so have ...
Electronic Design

Embedded: Module Blends USB With FPGA

Want to build a custom USB-based interface such as a USB-to-GPIB bridge? Check out the ZestSC1. The 7.5- by 12.5-cm module contains a USB controller, a Xilinx Spartan-3 1000 FPGA, 8 Mbytes of SRAM, ...
Electronic Design

GOEPEL Debuts FPGA JTAG I/O Modules

May 3, 2012. GOEPEL electronics has introduced ChipVORX Module, an FPGA based I/O module product line. The new modules are controlled via a standard TAP, enabling access to the entire ChipVORX ...
Design-Reuse

Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing

Today, Xilinx unveiled three new series of FPGAs all based on 28nm process technology from Samsung and TSMC. The three families are called the Virtex-7, Kintex-7, and Artix-7 series. All three FPGA ...
Design-Reuse

Solving FPGA I/O pin assignment challenges

A few weeks ago we looked at an article on Replacing obsolete video game circuits with Xilinx CPLDs, and now I'm delighted to have the opportunity to present the following piece from the Third Quarter ...