EDN

SystemVerilog Reference Verification Methodology: VMM Adoption

The larger and more complex that system-on-chip (SoC) designs grow, the more verification dominates the development process. In fact, effective design reuse puts even more pressure on the verification ...
Design-Reuse

AMIQ EDA Introduces Duplicate Code Detection in Its Verissimo SystemVerilog Testbench Linter

AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis ...
Design-Reuse

SystemVerilog 3.1 adds assertions and testbench automation

The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. It eliminates many of Verilog's past limitations, ...
Electronic Design

Tool Automates Generation Of SystemVerilog Testbenches

THE SYSTEMVERILOG INFRASTRUCTURE is built out further with Synopsys' introduction of Pioneer-NTB. This testbenchautomation tool delivers native SystemVerilog testbench generation to users of ...
Electronic Design

Find the Fastest Route to Portable Stimulus Tests with SystemVerilog

The new Accellera Portable Stimulus Specification language offers advantages such as portability across verification levels and greater test-creation productivity. The Portable Stimulus Specification ...
Semiconductor Engineering

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation

I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification ...
Semiconductor Engineering

Testbench Acceleration Performance Demystified

Part 2 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three ...
Business Wire

SpringSoft’s Verdi Debug Software Expands Verification Interoperability with Comprehensive UVM Support

HSINCHU, Taiwan--(BUSINESS WIRE)--SpringSoft, Inc., a global supplier of specialized IC design software, today announced comprehensive support for the Universal Verification Methodology (UVM) with its ...
EDN

SystemVerilog 3.1 adds assertions and testbench automation

The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. It eliminates many of Verilog's past limitations, ...