It has long been a goal to put realistic prototypes or models into system developer's hands as soon as possible. This has been accomplished with FPGAs, C language models and sometimes co-simulation ...

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all promised by version 5.0 of the VERA ...

Survey hardware design teams and you’ll find that the old saw is true: anywhere from 60% to 80% of the overall design cycle is consumed not with design itself, but rather with the nerve-wracking ...