• VHDL Design: Each logic gate is implemented using VHDL, a hardware description language that provides an abstraction for designing digital systems. • Simulation: The designs are simulated using ...
University Project I made during my EEE3104 Digital Electronics Lab OEL. First I did it in Quartus Simulation then Hardware. Working Principle: The smart room automation system functions based on the ...
In this project am going to show you how you can simulate a three-line-input eight-line-output decoder using the NI Multisim EDA. I made a design of the three-line input to eight-line output ...
Comparison of Gate-Level Techniques for Mitigation of Single Event Transients in Combinational Logic
Abstract: In this paper, the gate-level techniques for mitigation of Single Event Transients (SETs) in combinational circuits have been analyzed. The main objective was to compare the SET mitigation ...
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